The present invention relates generally to the field of data communication. More particularity, the present invention concerns a generic design and methodology of a new family of Bipolar Integrated Circuits (IC) that is capable of moving data up to a speed of 40 Gbit/Sec or higher when implemented on Silicon with a 0.18 xcexcm or lower wafer process. Thus, its direct applications include a variety of subsystem and system functions such as Master Slave D-type Flip Flop (MS-DFF), Divider, Bang Bang Phase Detector (BBPD), Frequency Detection (FD), Phase and Frequency Detection (PFD), Voltage Controlled Oscillator (VCO) and Phase Locked Loop (PLL) in an optical switch IC for data communication.
Optical fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec.
However, short of a completely optical communication system, the practically realizable bandwidth of fiber optical communication systems has been limited by the need of signal conversion between optical and electrical domain and the associated electronics hardware. While the usage of CMOS (Complementary Metal Oxide Semiconductor) ICs, having a moderate speed capability, has already migrated into the electronics hardware for optical communication systems due to their advantage of low manufacturing cost, low operating power consumption, low supply voltage requirement and fairly good circuit density, Bipolar technology, having a speed higher than CMOS technology, should still be employed where an even higher speed beyond the CMOS capability is needed.
Notwithstanding the employment of Bipolar technology, to approach its fundamental speed capability in real circuits for such ultra high speed applications, a balanced systems design methodology must be developed. Khaled and Elmasry published analysis and optimization of two-level, series-gated CML (Current Mode Logic) and ECL (Emitter Coupled Logic) high-speed Bipolar circuits with an analytical approach including transistor parasitics and transistor size variation between different levels to maximize their operating speed, albeit no actual output waveforms were presented (see Khaled M. Sharaf and Mohamed I. Elmasry, IEEE Journal on Solid-State Circuits, Vol. 31, No. 2, February 1996). While mentioning the possibility of a circuit optimization procedure based upon SPICE simulations, the Khaled publication stated that this simulation procedure requires a very large number of simulation runs to cover the related design space thus was difficult to practice.
The present invention is directed to a new family of Bipolar ICs and a generic design methodology of designing this new family of Bipolar ICs capable of moving data up to a speed of 40 Gbit/Sec when implemented on Silicon with a 0.18 xcexcm or lower wafer process.
The first objective of this invention is to achieve a generic design and methodology for a family of Bipolar ICs with a reduced amount of signal ripple after the respective logic signal levels are reached following a switching operation.